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Dettaglio pubblicazione

2016, 2016 International Conference on High Performance Computing and Simulation, HPCS 2016, Pages 42-47

CPU-core frequency scaling for efficient thread scheduling in transactional memories (04b Atto di convegno in volume)

DI SANZO Pierangelo, Ciciani Bruno

Transaction Memory systems may suffer from performance degradation when the concurrency level grows. The transaction abort rate caused by high concurrency may be detrimental to energy efficiency as well. Thread scheduling techniques, which proactively block some threads to optimize the concurrency level, help to reduce these phenomena. In this paper, we show that the efficiency of mechanisms used by tread schedulers for blocking/unblocking concurrent threads can be improved using CPU-core frequency scaling options offered by modern hardware systems. Particularly, we study a low-frequency busy waiting approach, in which blocked threads scale down the frequency of CPU-cores where they are running. We compare this approach with two commonly used approaches by thread schedulers, and we demonstrate that it achieves the best results in term of both performance and energy efficiency.
ISBN: 9781509020881; 978-1-5090-2089-8
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